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74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
November 1992 Revised March 2005
74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
Features
s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching, noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:
Order Number 74ABT374CSC 74ABT374CSCX_NL (Note 1) 74ABT374CSJ 74ABT374CMSA 74ABT374CMTC 74ABT374CPC Package Number M20B M20B M20D MSA20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names D0-D7 CP OE O0-O7 Data Inputs Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input (Active LOW) 3-STATE Outputs Description
(c) 2005 Fairchild Semiconductor Corporation
DS011510
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74ABT374
Functional Description
The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops.
Function Table
Inputs OE H H H H L L L L CP H D L H L H L H L H Internal Q NC NC L H L H NC NC Outputs O Z Z Z Z L H NC NC Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data Function

H H
H
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition NC No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ABT374
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) twice the rated IOL (mA)
65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100mV/ns
40qC to 85qC 4.5V to 5.5V
0.5V to 5.5V 0.5V to VCC
150 mA 500 mA
10V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 5)
Note 4: For 8-bit toggling, ICCD 0.8 mA/MHz. Note 5: Guaranteed, but not tested.
Min 2.0
Typ
Max 0.8
Units V V V V V
VCC
Conditions Recognized HIGH Signal Recognized LOW Signal
1.2
2.5 2.0
Min Min Min Min Max Max Max 0.0
IIN IOH IOH IOL VIN VIN VIN VIN VIN IID
18 mA 3 mA 32 mA
64 mA 2.7V (Note 5) VCC 7.0V 0.5V (Note 5) 0.0V 1.9 PA, All Other Pins Grounded 2.7V; OE 0.5V; OE 0.0V VCC 5.5V; All Others VCC or GND 2.0V 2.0V
VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT
0.55 1 1 7
V
PA PA PA
V
1 1
4.75 10
PA PA
mA
0 5.5V VOUT 0 5.5V VOUT Max Max 0.0 Max Max Max Max VOUT VOUT VOUT
10 100 275
50 100 50 30 50 2.5 2.5 2.5
PA PA PA
mA
All Outputs HIGH All Outputs LOW OE VI VCC; All Others at VCC or GND VCC 2.1V VCC 2.1V VCC 2.1V
PA
mA mA mA mA/
Enable Input VI Data Input VI Outputs OPEN OE
All Others at VCC or GND No Load 0.30 MHz Max GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
3
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74ABT374
DC Electrical Characteristics
(SOIC package) Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage Min Typ 0.5 Max 0.8 Units V V V V 0.8 V VCC 5.0 5.0 5.0 5.0 5.0 TA TA TA TA TA Conditions CL 50 pF, RL 500:
25qC (Note 6) 25qC (Note 6) 25qC (Note 7) 25qC (Note 8) 25qC (Note 8)
1.3
2.5 2.0
0.9
3.0 1.6 1.3
Note 6: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. Note 7: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 8: Max number of data inputs (n) switching. n 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package) TA Symbol Parameter Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable Time 150 2.0 2.0 1.5 1.5 1.5 1.5 VCC CL
25qC 5.0V
50 pF Typ 200 3.2 3.3 3.1 3.1 3.6 3.4 5.0 5.0 5.3 5.3 5.4 5.4 Max
TA VCC
55qC to 125qC
4.5V to 5.5V 50 pF Max 6.6 7.6 5.7 7.2 7.2 7.0
TA
40qC to 85qC
4.5V to 5.5V 50 pF Max MHz 5.0 5.0 5.3 5.3 5.4 5.4 ns ns ns Units
VCC
CL Min 150 1.4 2.0 0.8 1.5 1.3 1.0
CL Min 150 2.0 2.0 1.5 1.5 1.5 1.5
AC Operating Requirements
TA Symbol Parameter VCC CL Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Pulse Width, CP HIGH or LOW 1.5 1.5 1.0 1.0 3.0 3.0
25qC 5.0V
50 pF Max
TA
55qC to 125qC
4.5V to 5.5V 50 pF Max CL Min 2.5 2.5 2.5 2.5 3.3 3.3
TA
40qC to 85qC
4.5V to 5.5V 50 pF Max ns ns ns Units CL
V CC
VCC
Min 1.0 1.5 1.0 1.0 3.0 3.0
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74ABT374
Extended AC Electrical Characteristics
(SOIC Package) TA
40qC to 85qC
4.5V to 5.5V 50 pF CL
TA VCC
40qC to 85qC
4.5V to 5.5V 250 pF CL
TA
40qC to 85qC
4.5V to 5.5V 250 pF Units CL
VCC Symbol Parameter
VCC
8 Outputs Switching (Note 9) Min tPLH tPHL tPZH tPZL tPHZ tPZL Output Disable Time Propagation Delay CP to On Output Enable Time 1.5 1.5 1.5 1.5 1.0 1.0 Max 5.7 5.7 6.2 6.2 5.5 5.5 Min 2.0 2.0 2.0 2.0
(Note 10) Max 7.8 7.8 8.0 8.0 (Note 12)
8 Outputs Switching (Note 11) Min 2.0 2.0 2.0 2.0 (Note 12) Max 10.0 10.0 10.5 10.5 ns ns ns
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 12: The 3-STATE delay Time is dominated by the RC network (500:, 250 pF) on the output and has been excluded from the datasheet.
Skew
(Note 17)
TA
(SOIC Package)
40qC to 85qC
4.5V-5.5V 50 pF CL
TA
40qC to 85qC
4.5V-5.5V 250 pF Units CL
VCC Symbol Parameter
VCC
8 Outputs Switching (Note 13) Max tOSHL (Note 15) tOSLH (Note 15) tPS (Note 14) tOST (Note 15) tPV (Note 16) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH-HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 1.0 1.0 1.8 2.0 2.5
8 Outputs Switching (Note 14) Max 1.8 1.8 4.3 4.3 4.6 ns ns ns ns ns
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 17: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Capacitance
Conditions Symbol CIN COUT (Note 18) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0
1 MHz, per MIL-STD-883, Method 3012.
Units pF pF V CC V CC 0V 5.0V
(TA
25qC)
Note 18: COUT is measured at frequency f
5
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74ABT374
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tw 500 ns tr 2.5 ns
FIGURE 2. VM
1.5V
tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74ABT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74ABT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
9
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74ABT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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